＜数字小IP设计＞ 二：带读使能的总线组件；带位选小组件；单bit线采集多bit数据的data

module BUS_1 # (parameter RESET = 1'b0，width = 8) ( input clk_i, input rst_i, input en_i, input [width-1:0] dat_i, output reg [width-1:0] dat_o); always @ (posedge clk_i or posedge rst_i) begin if (clk_i) dat_o <= {width{RESET}}; else if(en_i) dat_o <= dat_i; else dat_o <= dat_o; end endmodule module BUS_2 # (parameter RESET = 1'b0，width = 32) ( input clk_i, input rst_i, input [3:0] be_i, input [width-1:0] dat_i, output reg [width-1:0] dat_o); always @ (posedge clk_i or posedge rst_i) begin if (clk_i) dat_o <= {width{RESET}}; else begin if(be_i[0]) dat_o[7:0] <= dat_i[7:0]; if(be_i[1]) dat_o[15:8] <= dat_i[15:8]; if(be_i[2]) dat_o[23:16] <= dat_i[23:16]; if(be_i[3]) dat_o[31:24] <= dat_i[31:24]; end end endmodule module BUS_3 # (parameter RESET = 0，width = 8) ( input clk_i, input rst_i, input [width-1:0] width_i, input en_i, output wire en_o); reg en; reg [width-1:0] count; always @(posedge clk_i) en <= en_i; wire flag = en_i & ~en; always @ (posedge clk_i or posedge rst_i) begin if(rst_i) count <= 0; else if (flag) count <= 1; else if(count == width_i) count <= 0; else if (count != 0) count <= count + 1; end assign en_o = count != 0 && ~ flag; endmodule

BUS_3的作用是当我们使用单比特信号线采集多比特信号线中所有的数据的时候（相同时钟域），因为一般会有一位作为有效信号（使能位），剩下的线上均为有效信号，将数据线的数量输入模块，就可以得到所需剩余数据周期宽度的使能信号。