题目：使用case语句设计八功能的算术运算单元（ALU），其输入信号a和b均为4位，功能选择信号select为3位，输出信号out为5位。算术运算单元ALU所执行的操作与select信号有关，具体关系见下表。
Verilog描述：
module ALU(a,b,select,out); input [3:0] a,b; input [2:0] select; output reg [4:0] out; always @ (select or a or b) begin case(select) 3'b000: out = a; 3'b001: out = a + b; 3'b010: out = a - b; 3'b011: out = a / b; 3'b100: out = a % b; 3'b101: out = a << 1; 3'b110: out = a >> 1; 3'b111: out = (a > b); default: out = 5'bx; endcase end endmodule测试程序：
`timescale 1ns/1ps module ALU_tb; reg [3:0] a,b; reg [2:0] select; wire [4:0] out; ALU alu1(a,b,select,out); initial begin a<=4'b0000;b<=4'b0000;select<=3'b000; end initial fork //并行块 #10 a <= 4'b0110; #20 a <= 4'b0100; #15 b <= 4'b0001; #30 b <= 4'b0010; join initial fork #10 select <= 3'b000; #20 select <= 3'b001; #30 select <= 3'b010; #40 select <= 3'b011; #50 select <= 3'b100; #60 select <= 3'b101; #70 select <= 3'b110; #80 select <= 3'b111; #10 a <= 4'b0110; #20 a <= 4'b0100; #15 b <= 4'b0001; #30 b <= 4'b0010; join endmodule仿真结果：
