chisel中如何使用BlackBox

chisel中的BlackBoxBlackBox实现格式BlackBox例化格式

chisel中的BlackBox

源文章来自于： https://chipyard.readthedocs.io/en/latest/Customization/Incorporating-Verilog-Blocks.html 并做了一些修改

BlackBox的使用可以在chisel中嵌入原有使用Verilog所写的模块。

BlackBox实现格式

module GCDMMIOBlackBox #(parameter WIDTH) ( input clock, input reset, output input_ready, input input_valid, input [WIDTH-1:0] x, input [WIDTH-1:0] y, input output_ready, output output_valid, output reg [WIDTH-1:0] gcd, output busy ); ...... endmodule

对应的chisel BlackBox实现方式：

class GCDMMIOBlackBox(val wd: Int) extends BlackBox(Map("WIDTH" -> wd)) { val OtherInnerPara = ... val io = IO(new Bundle{ val clock = input ( Clock() ) val reset = input ( Bool() ) val input_ready = output( Bool() ) val input_valid = input ( Bool() ) val x = input ( UInt(wd.W) ) val y = input ( UInt(wd.W) ) val output_ready = input ( Bool() ) val output_valid = output( Bool() ) val gcd = output( UInt(wd.W) ) val busy = output( Bool() ) }) }

BlackBox例化格式

class GCDModule(val params: GCDParams) extends Module { val io... val x = Reg(UInt(params.width.W)) val y = Wire(new DecoupledIO(UInt(params.width.W))) val gcd = Wire(new DecoupledIO(UInt(params.width.W))) val status = Wire(UInt(2.W)) //此处例化BlackBox val impl = Module(new GCDMMIOBlackBox(params.width)) //时钟和复位连接 impl.io.clock := clock impl.io.reset := reset.asBool //信号连接 impl.io.x := x impl.io.y := y.bits impl.io.input_valid := y.valid y.ready := impl.io.input_ready gcd.bits := impl.io.gcd gcd.valid := impl.io.output_valid impl.io.output_ready := gcd.ready status := Cat(impl.io.input_ready, impl.io.output_valid) io.gcd_busy := impl.io.busy }